{"id":1119,"date":"2018-01-03T15:45:56","date_gmt":"2018-01-03T14:45:56","guid":{"rendered":"https:\/\/www.eet.bme.hu\/en\/?page_id=1119"},"modified":"2018-01-04T13:27:06","modified_gmt":"2018-01-04T12:27:06","slug":"its","status":"publish","type":"page","link":"https:\/\/www.eet.bme.hu\/en\/rdi\/competences\/its\/","title":{"rendered":"ITS"},"content":{"rendered":"

Integrated Thermal Solutions Research Team<\/h1>
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Integrated microscale cooling structures<\/div>\n
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First generation integrated microscale heatsink structure<\/p><\/div>\n\n<\/div>\n<\/div>\n<\/section>\n\n

Injection locked oscillators<\/div>\n
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Frequency dividers are widely used in high-frequency digital (for example System-On-a-Chip) and analog radio frequency circuits. In telecommunications frequency dividers are most often used to synthesize the carrier signal accurately and fast. The carrier signals are turned out by so called frequency-synthesizers (for example PLL \u2013 Phase Locked Loop) which crucially includes frequency dividers. Low consumption, the ability to change the division ratio fast during the operation (even some thousand times per second, for example BlueTooth 1600 times per second) and robust operation is prominently important.<\/p>\n

As the integrity and the frequency of the digital integrated circuits have raised, new demands and expectations appeared. Since the area of the chips have continuously grown, the importance of the ability to use clock signals with different frequency at different locations on the chip have raised. Because of this, the clock signal synthesizer centers have to be able to produce signals with dynamically changeable frequency.<\/p>\n

The biggest challenge is to reduce the consumption of the circuits, because as the running frequencies of the integrated circuits raise, their dissipation raises as well, which leads to higher temperatures of the circuits during the running. When the temperature of the circuit increases, the operating points and threshold voltages of the transistors change, which leads to the changing of the delays in the digital circuits and it can cause failures in the operation.<\/p>\n

For these new challenges, using Injection Locked Oscillator (ILO) circuits can be a solution. The ILO circuits appeared in the past decade and still an active field of researches.<\/p>\n

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CMOS ring-oscillator with enabling input<\/em><\/p><\/div>\n

In our work I present the architecture and the functioning of different frequency divider circuits especially focusing on the ILOs. The goal of this work is to design an ILO that will be able to lock on the incoming highfrequency signal and can divide its frequency with the given division ratio. Furthermore, we design an ILO that can be connected to digital circuits to create a frequency divider with adjustable division ratio. During our\u00a0 research we will make on effort on reducing the effect of the deviation of the transistor parameters and the changing of the temperature to consider the design for manufacturability. Taking into account of the previous points we minimize the power consumption of the ILO to create a widely useable circuit.<\/p>\n

During our research we use the Cadence 6 integrated circuit design framework with the Austria Micro Systems 350 nm and 180 nm technologies.<\/p>\n\n<\/div>\n<\/div>\n<\/section>\n\n

CFD and multiphysical simulation<\/div>\n
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Our team<\/h3>
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