Design of a UVM compatible System Verilog VIP for PCI express Transaction Layer
The PCI express hardware is very complex and it requires many simulation resources. To speed up the functional verification a possible way can be to simulate only the upper PCI express layer with an active PCI express VIP.
Main tasks of the student:
- Get familiar with a typical UVM verification IP (VIP) architecture
- Get familiar with the related PCI express standards
- Implement the PCI express TLP VIP with the following features:
- Contains a class for TLP packets of the transaction layer in PCIe
- Is capable of creating/generating request TLPs for config/memory space reads/writes
- Is capable of creating/generating completion TLPs based on incoming request TLP
- Contains built-in protocol checking
- Contains built-in low level functional coverage
The topic is hosted by the hungarian office of Veriest.